This invention relates to a semiconductor device and, more particularly, to one having an address transition detector circuit (hereinafter called ATD circuit) in MOS memory devices or other storage devices.
An ATD circuit used in a MOS memory is typically configured to generate a one-shot pulse upon detection of any change in address and to supply the pulse to a control circuit which responsively controls circuits in the memory.
FIG. 5 is a partial circuit diagram of a conventional semiconductor device.
The conventional semiconductor device shown here includes an address buffer circuit 1 and an ATD circuit 2. As illustrated, an address line A designating a memory address is coupled to an address buffer circuit 1 and supplied therein to a plurality of serial delay buffer elements (inverter circuits) IN1 through IN7. Signals from respective elements of the address buffer circuit 1 are coupled switching elements (NMOS transistors) N1 through N4 provided in the ATD circuit 2 to detect changes in condition of the address line A. A PMOS transistor P1 in the ATD circuit 2 is of a type normally ON to function as pull-up means. In the address buffer circuit 1, a signal of the address line A is introduced into inverter circuits IN2 and IN1. The signal from the address line A is illustrated as signal a, and an output signal from the inverter circuit IN1 as signal c. An output signal from the inverter circuit IN6 resulting from signal a passing through the inverter delay circuits (IN2, IN4 and IN6) is illustrated as signal b, and an output signal from the inverter circuit IN7 resulting from signal c passing through the inverter delay circuits (IN3, IN5 and IN7) is illustrated as signal d.
On the other hand, the NMOS transistor N1 supplied with signal a through the gate and the NMOS transistor N2 supplied with signal b through the gate are connected in series to form a NAND logic for signal a and signal b. The NMOS transistor N3 supplied with signal c at through the gate and the NMOS transistor N4 supplied with signal d through the gate are connected in series to form a NAND logic for signal c and signal d. The serial circuit of the NMOS transistors N1, N2 and the serial circuit of NMOS transistors N3, N4 are connected in parallel to form an AND logic for these two NAND logic circuits. One end of the NMOS transistor N2 and one end of the NMOS transistor N3 in two serial circuits are connected to ground GND, and one end of NMOS transistor N1 and one end of NMOS transistor N3 are connected to one end of the PMOS transistor P1. The other end of the PMOS transistor P1 is connected to a power source Vcc. Output from the ATD circuit is an output signal Fa as an address transition detection signal.
FIGS. 6A-6G are timing charts showing operations of the circuit construction described above.
FIG. 6A shows a signal from the address line A (signal a). FIG. 6B shows an output signal from the inverter circuit IN6 (signal b) obtained by passing signal a through the inverter delay circuits (IN2, IN4, IN6). FIG. 6C shows an output signal from the inverter circuit IN1 (signal c). FIG. 6D shows an output signal from the inverter circuit IN7 (signal d) obtained by passing signal c through the inverter delay circuits (IN3, IN5, IN7). FIG. 6E shows a NAND logic state based on the NMOS transistors N1 and N2. FIG. 6F shows a NAND logic state based on the NMOS transistors N3 and N4. FIG. 6G shows an AND logic output (output signal Fa of the ATD circuit) of the states shown in FIGS. 6E and 6F.
Inverters IN1 through IN7 in the address buffer circuit 1 individually behave as delay elements having a constant gate delay time td, respectively. Therefore, signals a through d are different in polarity and timing as shown in FIGS. 6A through 6D. Introduced into the NMOS transistors N1 through N4 are different two pairs of true-value compensation signals from the address buffer circuit 1.
If the address line A changes at points of time, t1, t6 and t11, as shown in FIG. 6A, then the signal c is inverted at points of time t2, t7 and t12 after a delay of td, respectively. On the other hand, signal b obtained by delaying signal a by three times the gate delay time td in the inverter circuits IN2, IN4 and IN6 is inverted at t4, t9 and t14 as shown in FIG. 6B. Signal d obtained by delaying signal c by three times the gate delay time td in the inverter circuits IN3, IN5 and IN7 is inverted at t5, t10 and t15 as shown in FIG. 6D.
Therefore, the NAND logic obtained by the NMOS transistors N1 and N2 is established when both signals a and b exhibit high levels, and satisfies the condition for the low level as shown in FIG. 6E. The NAND logic obtained by the NMOS transistors N3 and N4 is established when both signals c and d exhibit high levels, and satisfies the condition for the low level as shown in FIG. 6F. As a result, output signal Fa is output from the ATD circuit 2 as a low-level signal from the point of time t1 to t4 and from t11 to t14 as shown in FIG. 6G on the basis of the AND condition of the NAND condition output of signals a and b and the NAND condition output of signals c and d. Therefore, individual portions of the memory circuit can be controlled by using the one-shot pulse signal obtained by transition of the address line A.
The one-shot pulse signal Fa is typically employed in a circuit for controlling initialization of data lines, such as equalization of data lines, precharging of data lines, and so forth. Initialization of a data line is means for resetting data before address transition still remaining on the data line to the initial level, when address transition takes place upon access to data, so that data output from a memory cell after the address transition be quickly output onto the data line. The initial level is a level determined by the data line load transistor. In most cases, when the data line load transistor is a PMOS transistor, it is the (Vcc) level. When the data line load transistor is an NMOS transistor, it is the (Vcc-Vth) level.
Explained below are behaviors for data line initialization upon address transition. FIG. 7 shows a general construction of a typical semiconductor device. The semiconductor device of this type includes an address line A, address buffer circuit 1, ATD circuit 2, data line initialization control circuit 3, and memory circuit 4. The memory circuit 4 includes data line load transistors T1, T2, data line equalize transistor Te, data line precharge transistors Tp1, Tp2, data lines Da and Db in a complementary relationship, memory cell MC and word line WL. Data line load transistors T1, T2, data line equalize transistor Te, data line precharge transistors Tp1 and Tp2 shown here may be NMOS transistors, respectively.
Next shown in FIG. 8 is a waveform diagram during operation of data lines in the semiconductor device shown in FIG. 7. Here are shown, particularly, the waveform of an output signal Di from the data line initialize control circuit 3 and waveforms in complementary data lines Da and Db.
When transition of the address line A takes place, a one-shot pulse signal Fa is output from the ATD circuit 2. The one-shot pulse signal Fa is introduced into the data line initialization control circuit 3 supplied with a decoded signal, etc., synthesized with the decoded signal, etc., and output as a one-shot pulse signal Di from the control circuit 3. The one-shot pulse signal Di is input to the data line equalize transistor Te and the data line precharge transistors Tp1, Tp2. The data line equalize transistor Te and the data line precharge transistors Tp1, Tp2 are changed ON by the one-shot pulse signal Di for a moment. As a result, data lien Da and data line Db are equalized by the data line equalize transistor Te. Simultaneously, data line Da and data line Db are precharged by the data line precharge transistors Tp1, Tp2 to the initial level, namely (Vcc-Vth) level. During the initializing period of the data lines, the word line after address transition is activated; and upon completion of initialization of the data lines, namely, at the same time when the one-shot pulse signal Di changes to the low level, and the data line equalize transistor Te and data line precharge transistors Tp1, Tp2 are changed to OFF, data from the memory cell MC after address transition is output onto the data line.
For reference, FIG. 9 shows a waveform diagram of data lines under operation upon access to data in a device without means for initializing data lines. As shown here, inversion of data line Da and data line Db are effected only by a small driving power of the memory cell, and much time is required for data inversion. It results in a great delay in access time.
As explained above, when address transition takes place, data lines are always reset by the data line initialize means to the (Vcc-Vth) level, which is the same as the level determined by data line load transistors. In this manner, data inversion of data lines are effected quickly, and quick access to data is realized.
As shown in the waveform diagram of FIG. 8, access to data is effectuated after the data lines are initialized, namely, after the one-shot pulse signal Di changes to the low level. That is, the access time depends upon the pulse width of the output signal Fa from the ATD circuit 2. When the pulse width of the output signal Fa of the ATD circuit 2 becomes longer, the access time tends to delay. However, if the pulse width of the output signal Fa from the ATD circuit 2 is made excessively short, then the data before the address transition remains on data lines, and results in delaying the data inversion time of the data lines and in delaying the access time.
In this manner, the pulse width of the output signal Fa of the ATD circuit 2, either too long or too short, causes a delay in access time, and it is difficult to set and maintain an appropriate pulse width. In general, the pulse width of the output signal Fa of the ATD circuit is designed and determined by simulation of IC operation. However, operative characteristics of a real device (IC as a product) do not always coincide with the result of the simulation. Even when an optimum pulse width is determined by the simulation, the real device may fail to provide the pulse width determined by the simulation.
Therefore, for preparation against such undesirable cases, IC be designed to enable adjustment of the ATD pulse width upon estimation of IC characteristics after fabrication. FIG. 10 shows a circuit for adjusting the ATD pulse width.
As shown in FIG. 10, previously prepared is a PMOS transistor P3 having W=5 .mu.m, which may be normally ON for example, in addition to normally ON-state PMOS transistors P1 and P2 having W=5 .mu.m connected to the output of the ATD circuit 2 to behave as pull-up means.
Here, "W" is the channel width of the diffusion layer of a transistor. FIGS. 11A and 11B are diagrams for explaining the channel width, in which FIG. 11A is a plan view, FIG. 11B is a cross-sectional view. A diffusion layer 111 and a gate electrode 112 of a transistor formed as illustrated, and the channel width is as shown here.
When an IC needs adjustment of the ATD pulse width, using a focusing ion beam apparatus (FIB apparatus), or the like, the output line (Fa) of the ATD circuit 2 is processed by connecting or cutting wirings W1 to W3 to change the size of the normally ON-state PMOS transistor operative as pull-up means and to thereby adjust the ATD pulse width.
In greater detail, if wires W1 and W2 are already connected, wire W3 is connected to the output line (Fa) of the ATD circuit 3 when the function as pull-up means with W=15 .mu.m is desired. When the function as pull-up means with W=5 .mu.m is desired, the ATD pulse width is adjusted by cutting the wire W2 from the output line (Fa) of the ATD circuit 2.
As explained above, for enabling adjustment of the pulse width of the output signal Fa of the ATD circuit 2, normally ON-state PMOS transistors P1, P2 and P3 are prepared to be re-combined by cutting or connecting the wiring on a real device by using a FIB apparatus, for example. However, adjustment of the pulse width in this manner involves the following problems.
The first problem lies in that only one pulse width and no other pulse width can be tried with a single IC sample because it is very difficult to re-process a device once processed because of the nature of the FIB apparatus. Therefore, to try a plurality of pulse widths, a corresponding number of IC samples must be prepared. Since IC samples must exhibit the same operative characteristics, there arises the need for selecting such IC samples by using a tester.
The second problem lies in that processing of a device by a FIB apparatus, or the like, does not always result in success. For example, for cutting aluminum wiring, which relies on irradiation of an ion beam to the aluminum wiring to scrape off a part of aluminum, shortage in irradiation time of the ion beam will result in failure to fully remove the aluminum wiring and to cut off the wiring, and an excessive irradiation time of the ion beam will result in removing the inter-layer insulating film under the aluminum wiring and in finally breaking the device when the ion beam reaches the substrate. As to connection of a wiring, an aluminum wiring, for example, is connected by making a hole in an inter-layer insulating film overlying the aluminum wiring by using an ion beam and by stacking tungsten or another metal in the hole by vapor deposition. However, similarly to the cutting process of aluminum wiring, it may result in failure, depending upon the irradiation time of the ion beam.
Thus, the process of cutting and connection of wiring on a device by a FIB apparatus, or the like, does not result in success, depending upon the selected irradiation time of the ion beam.
Summarizing the foregoing discussion, previously prepared normally-ON PMOS transistors P1, P2 and P3 are recombined for adjusting the pulse width of the output signal Fa of the ATD circuit, and the recombination is made by cutting or connecting a wiring on a real device by using a FIB apparatus, or the like. However, the first problem with this method is the need for an additional process of selecting IC samples having the same operative characteristics through a tester to try different pulse widths, and the second problem is that devices cannot be processed successfully unless the irradiation time of an ion beam in a FIB apparatus is set within a strictly appropriate range.